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High Power Replaceable Unit (LRU) ・Hot swappable ・Modular design for user replacement ・Front panel status indicators on front panel ・MIL-STD-461F MIL-STD-704F適合

・Continuum HPEC Software Platform Features 　　・Processor abstraction (Intel®, Power Architecture™, FPGA and GPGPU) 　　・DMA control and fabric handshake 　　・Zero-Copy data transfers 　　・Middleware/user layer abstraction (OpenMPI and other OS function calls) 　　・Supports DMA controlled diagnostics utilities and tools 　　・Low latency high speed (up to 20Gbits/s) application to application data transfers ・OFED Features 　　・Operating system abstraction (Linux®, Windows®, OpenSolaris™) 　　・Fabric abstraction (InfiniBand™, 10 Gigabit Ethernet, and Serial RapidIO®) 　　・Middleware abstraction (OpenMPI, OpenSM, and Intel MPI) 　　・Processor abstraction (Intel®, Power Architecture™, FPGA and GPGPU) 　　・DMA control and fabric handshake 　　・Zero-Copy data transfers 　　・Supports DMA controlled diagnostics utilities and tools 　　・Low latency high speed (up to 20Gbits/s) application to application data transfers

600 Mbytes per second I/O transfer rate via the front panel connector (LVDS transceivers). 400 Mbytes per second PCI burst transfer rate over 300 Mbs sustained Upgrade in future to 600 MBps sustained Can interface to a wide variety of external high-speed devices. "Deep FIFO buffers" (4 Megabytes) allow data bursts to be transferred over the PCI bus. 64-Bit data transfers on the PCI bus. On-board cable controller, FIFOs, and DMA engine provide for continuous data transfer. Data input/output clock rate up to 150 MHz. 64-Bit, 66 MHz PCI v2.2 compliant Cable data input/output width of 32 bits. 8 bi-directional signals can be used as clocks and/or handshaking protocol.

Four Lane PCI Express (PCIe4) Interface PCIe Data transfers to/from Memory Buffers at speeds approaching 800 MByte/sec Large 512 MByte (128M x 32) Transmit/Receive Memory Buffers 500 MByte/sec Transfers to/from the Board via LVDS Front Panel Interface Bidirectional LVDS Transceivers provide for Multipoint Applications Half Duplex Operation - Transmit or Receive Mode Programmable Transmit Clock from 125MHz down to 50Hz Programmable Polarity for Clock and Data Valid Signals Five General Purpose IO Signals, including Interrupt Inputs Optional Receive Ready Signal for Data Throttling Interrupts available including DMA Completion, Transfer Status, Cable Status 80 pin Front Edge I/O Connector Standard Twisted Pair Ribbon Cables and Custom Cables available Windows and Linux drivers Available

Four SERDES to QSFP28 to allow for high-speed multi-protocol communicate via Fiber or Copper •On board PLL to lock to input clock for synchronization •Two channels SAR ADC based on LTC2378, 20-bit at one MSPS •Two channels DAC based on AD5791, 20-bit

The PMC64-HPDI32B board provides the same capabilities as PMC64-HPDI32A versions with Huge FIFO Buffers. Different buffer sizes are available from 32Mbytes to 256Mbytes providing 32-bit buffering of 8M to 64M samples, respectively. The buffers can be configured on the fly as all transmit, all receive, or half of each. This provides a 64-bit 66MHz PCI interface capable of 400Mbytes/sec. The board is useful as a general-purpose DMA interface to a variety of external peripherals. The DMA engine is capable of transferring data to/ from Host memory using D64 block transfers, while the FIFO memory provides continuous transmission of data without interrupting the DMA transfers or requiring intervention from the Host CPU. The cable interface is flexible, transmits and receives data at up to 200M bytes/sec per second, and has 7 bi-directional programmable handshake lines to allow easy interfacing to most digital I/O peripherals

Complete transceiver signal chain solution using Dual Analog Devices (ADRV9009) on a single-wide FMC •Frequency range 75 MHz to 6 GHz, receiver BW up to 200 MHz and transmitter synthesis BW up to 450 MHz •Onboard clocking with multi-card synchronization capability. BSP sync’s dual ADRV9009 as standard •Compatible with Analog Devices design tools for ADRV9009

The PMC-HPDI32B-COS is a 32-bit parallel Change of State Detection board featuring high speed RS485 interface transceivers. The Change of State detection is can be customized to ignore specific bits and to provide an interrupt after a specified number of change of state events have occurred. The board will also function as a simple Logic Analyzer with a configurable trigger value and mask. The sample rate for both Change of State and Logic Analyzer is programmable from 20MHz down to 300Hz. Received values are buffered in an 8K deep on-board FIFO which is easily accessed by the integrated a DMA Controller. After the DMA is initialized and started, the host CPU will be free to proceed with other duties and need to respond only to interrupts. The DMA controller is capable of transferring data to host memory using D32 transfers; whereas the FIFO memory provides a means for continuous transmission of data without interrupting the DMA or requiring intervention from the host CPU.

The PMC64-HPDI32ALT board is a flexible bi-directional 32-bit digital I/O board that transmits and receives data from 20 Mbytes (TTL I/O) to 200 Mbytes (LVDS) per second. This board provides a 64-bit 66MHz PCI interface capable of 400Mbytes/sec burst rate. The board is useful as a general-purpose DMA interface to a variety of external peripherals. The DMA engine is capable of transferring data to/ from Host memory using D32 block transfers, while the FIFO memory (up to One Mbyte of total FIFO) provides continuous transmission of data without interrupting the DMA transfers or requiring intervention from the Host CPU. The board has 7 bi-directional programmable handshake lines to allow easy interfacing to most digital I/O peripherals

The PMC-HPDI32A board is a fast and flexible bi-directional 32-bit digital I/O board that transmits and receives data up to 80 Mbytes (differential I/O) or up to 200 Mbytes (Pseudo ECL I/O) per second. The board is useful as a general purpose DMA interface to a variety of external peripherals. The DMA engine is capable of transferring data to/from Host memory using D32 block transfers, while the FIFO memory (up to One Mbyte of total FIFO) provides continuous transmission of data without interrupting the DMA transfers or requiring intervention from the Host CPU. The board has 7 bi-directional programmable handshake lines and eight pre-configured software selectable interface protocols to allow easy interfacing to most digital I/ O peripherals. Available transceivers are RS485/422 and PECL. For TTL and LVDS transceiver versions, please see the PMC64-HPDI32ALT.