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Precision 16-Bit simultaneously-clocked analog outputs: R-2R DAC per channel  Available with either 16 single-ended outputs, or 16 balanced-differential outputs  Software-selectable ranges of ±10V, ±5V. Optionally 0 to +10V, or 0 to +5V.  Output clocking rates from zero to 500K samples per second per channel.  Optional Outputs-Disconnect feature supports multiple-board redundancy, and eliminates outputs activity during autocalibration  Remote ground-sense input minimizes the effects of interground potentials  Supports both Block-mode and Demand-mode DMA transactions  2 Megasample output data FIFO buffer; Configurable as open or closed (circular)  Simultaneous output clocking  Multiboard synchronization supported  Continuous and Triggered-Burst output modes support seamless waveform sequencing  Data clocking rate controlled internally or externally  High accuracy ensured by on-demand Autocalibration of all channels  Single-width PMC form facto

24 wide-range differential 24-Bit simultaneously-sampled analog input channels.  Sample rates from 1.0 Kilosamples per second (KSPS) to 200 KSPS per channel.  Synchronous operation; all channels clocked simultaneously.  Software-selectable analog input ranges of ±10V, ±1V, ±100mV, ±10mV. (Optional ±10V, ±5V, ±2V, ±1V ranges, or ±5V, ±0.5V, 50mV, ±5mV ranges also available).  Delta-Sigma input conversion minimizes or eliminates the need for antialias filtering.  Low noise: 106dB typical dynamic range.  256K-sample analog input FIFO buffer.  Sample clock source selected as internal or external.  Hardware sync and clock I/O for multiboard synchronization.  On-demand autocalibration ensures DC offset precision as well as AC performance.  Conforms to PCI Express Specification revision 1.0a, single-lane.  DMA engine supports both block-mode and demand-Mode transfers.  Integrated DC/DC conversion and regulation of precision internal supply voltages.

・3x Gigabit Ethernet, and 2x 10/100 ・6U VME SBC ・Up to 2 GB DDR2 SDRAM with ECC for each node ・Power Architecture 8641D/8641 or 8640D/8640 ・Dual or Single Node Processor Configuration ・VME64 2eSST interface ・VTM23 Rear Transition Module ・Download our Ruggedization Levels guide (also available from the Downloads tab)

 Four 20-Bit analog output channels.  Software-selectable output configuration: 2-Wire Single-ended or 3-Wire Differential.  Simultaneous Clocking; Individual 20-Bit R-2R DAC per output channel.  Clocking rates from zero to 500KSPS.  Software-selectable fullscale output ranges: ±10V and ±5V.  8th-Order reconstruction filter in each output channel.  Optional Outputs Disconnect feature ensures quiet outputs during autocalibration and selftest operations. Software control. Adds 1-Ohm to R-out.  Remote ground sensing to minimize single-ended errors.  On-demand autocalibration of all channels.  256K-sample output FIFO buffer.  Internal sample rate generator with 24-Bit rate divider.  Hardware trigger and clock I/O for multiboard synchronization.  Eight Bidirectional digital TTL I/O lines.  Conforms to PCI Express Specification revision 1.0a, single-lane.  Standard PCI Express Short-card form factor.  DMA Engine supports block-mode and demand-mode transfers in two DMA channels.

Six Differential Analog Inputs with dedicated 18-Bit ADC per channel  True Simultaneous Sampling of all inputs from Zero to 12MSPS per channel  2.0 Megasample input data FIFO buffer  SAR Architecture; No minimum sample rate; Minimum Latency  Selectable Input Ranges: (Order Wideband or High-Level) Wideband: ±2.5V, ±1.25V, ±0.625V ; or High-Level: ±10V, ±5V, ±2.5V  Miniature MMCX coaxial system connectors for analog inputs and timing I/O.  Hardware Clock and Sync I/O for multiboard operation  Timing Controlled by internal rate generators, by software clocking, or externally  DMA Engine minimizes bus congestion  Dual Power Conversion for optimum internal power voltage integrity  Internal on-demand Autocalibration of all channels  PCI Express control interface  XMC form factor  Extended-temperature version available

 Precision 16-Bit simultaneously-clocked analog outputs: R-2R DAC per channel  Available with either 64 single-ended outputs, or 32 balanced-differential outputs  Software-selectable ranges of ±10V, ±5V. Optionally 0 to +10V, or 0 to +5V.  Output clocking rates from zero to 500K samples per second per channel.  Reconstruction filter in each output channel: 6th order Lowpass, 300Hz-100kHz.  Optional Outputs-Disconnect feature supports multiple-board redundancy, and eliminates outputs activity during autocalibration  Remote ground-sense input minimizes the effects of interground potentials  Supports both Block-mode and Demand-mode DMA transactions  256K-Sample output data FIFO buffer; Configurable as open or closed (circular)  Simultaneous output clocking, with emulated sequential outputs also supported  Multiboard synchronization supported  Continuous and Triggered-Burst output modes support seamless waveform sequencing  Data clocking rate controlled internally or externally  High accuracy ensured by on-demand Autocalibration of all channels  x1 Link PCI Express Port operating at 2.5Gbps  Available on multiple form factors, including PCI, and cPCI, as well as PC104-Plus, PMC, PCIX and cPCIX with reduced channel count. Contact Sales for availability

8 Differential Analog Inputs with Dedicated 12-Bit, 2.0 MSPS ADC per Channel True Simultaneous Sampling of all Inputs; Minimum Data Skew Sampling Rates to 2.0 MSPS per Channel (16 MSPS Aggregate Rate) Input Ranges: ±1V, ±100mV; Factory Configured. Custom ranges to ±10V. 64-Ksample Analog Input FIFO Data Buffer Supports DMA Transfers in Two Channels in Block-Mode or Demand-Mode 4 Analog Output Channels with Direct Register Access 16-Bit Bidirectional Digital I/O Port Sampling Controlled by Internal Rate Generator, by Software Trigger, or Externally On-Demand Internal Autocalibration Hardware Sync I/O for Multiboard Operation Integral Dual-Conversion Precision Analog Power Supplies Completely Software-Configurable; No Field Jumpers Conforms to PCI Local Bus Specification, Revision 2.3, with Universal Signaling

The 12AIO provides a cost effective high-speed 12-bit analog input/output and digital I/O board. Four analog output channels (at 300,000 samples/ sec per channel) are updated either synchronously or asynchronously, and support arbitrary waveform generation. The analog inputs are configurable as either 32 single-ended or 16 differential inputs, and can be scanned continuously or in bursts. Inputs and outputs have a common software selected range of ±10V, ±5V or ±2.5V, and are accessed through independent 32K-sample FIFO buffers. Internal auto-calibration networks permit calibration to be performed without removing the board from the system. Software controlled test configurations include a loop-back mode for monitoring all analog output channels.

The 16-Bit PMC66-16AISS16AO2 analog I/O module samples and digitizes 16 input channels simultaneously at rates up to 1.0 million samples per second per channel, and the resulting 16-bit sampled data is available to the PCI bus through a 256K-Sample FIFO buffer. Sampling can be controlled in groups of 1 through 16 channels, and the sample clock can be generated either from an internal rate generator, or by software or an external source. Both burst and continuous sampling modes are supported, and input ranges are software-selectable as ±10V, ±5V or ±2.5V. The inputs are divided into two channel groups, with an independent software-controlled range assignable to each group. Two analog output channels provide software-selected output ranges of ±2.5V, ±5V or ±10V that are independent of the input range assignments. The outputs are accessed either directly through two dedicated control registers, or through a 256K-Sample FIFO buffer for waveform generation. Four bidirectional digital I/O lines are programmable as inputs or outputs. On-demand autocalibration determines and applies offset and gain correction values for all input and output channels. A selftest input switching network routes output channels or calibration reference signals to the analog inputs, and permits board integrity to be verified by the host.

Analog Inputs: 8 Differential Analog Inputs with Dedicated 16-Bit ADC per Channel True Simultaneous Sampling of all Inputs to 2.0 MSPS per channel Analog Outputs: 4 Single-Ended Analog Outputs with Dedicated 16-Bit DAC per Channel Simultaneous Output Clocking Rates to 1.0 MSPS per Channel Common Analog I/O Features: Selectable Input/Output Ranges: ±10V, ±5V, ±2.5V Independent 256-K sample Input and Output FIFO Data Buffers Hardware Clock and Sync I/O for Multiboard Operation Internal Power Conversion; Single 5-Volt Power Requirement DMA Engine Minimizes Bus Congestion Timing Controlled by Internal Rate Generator, by Software Clocking, or Externally Internal Autocalibration 16-Bit Bidirectional TTL Digital I/O Port 66 MHz 32-Bit PCI Support, with Universal Signaling