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The 16-Bit PMC66-16AISS16AO2 analog I/O module samples and digitizes 16 input channels simultaneously at rates up to 1.0 million samples per second per channel, and the resulting 16-bit sampled data is available to the PCI bus through a 256K-Sample FIFO buffer. Sampling can be controlled in groups of 1 through 16 channels, and the sample clock can be generated either from an internal rate generator, or by software or an external source. Both burst and continuous sampling modes are supported, and input ranges are software-selectable as ±10V, ±5V or ±2.5V. The inputs are divided into two channel groups, with an independent software-controlled range assignable to each group. Two analog output channels provide software-selected output ranges of ±2.5V, ±5V or ±10V that are independent of the input range assignments. The outputs are accessed either directly through two dedicated control registers, or through a 256K-Sample FIFO buffer for waveform generation. Four bidirectional digital I/O lines are programmable as inputs or outputs. On-demand autocalibration determines and applies offset and gain correction values for all input and output channels. A selftest input switching network routes output channels or calibration reference signals to the analog inputs, and permits board integrity to be verified by the host.

Analog Inputs: 8 Differential Analog Inputs with Dedicated 16-Bit ADC per Channel True Simultaneous Sampling of all Inputs to 2.0 MSPS per channel Analog Outputs: 4 Single-Ended Analog Outputs with Dedicated 16-Bit DAC per Channel Simultaneous Output Clocking Rates to 1.0 MSPS per Channel Common Analog I/O Features: Selectable Input/Output Ranges: ±10V, ±5V, ±2.5V Independent 256-K sample Input and Output FIFO Data Buffers Hardware Clock and Sync I/O for Multiboard Operation Internal Power Conversion; Single 5-Volt Power Requirement DMA Engine Minimizes Bus Congestion Timing Controlled by Internal Rate Generator, by Software Clocking, or Externally Internal Autocalibration 16-Bit Bidirectional TTL Digital I/O Port 66 MHz 32-Bit PCI Support, with Universal Signaling

The PMC-16AIO168 provides a cost effective, high-speed 16-bit analog input/ output and digital output board. Eight analog output channels (at 300,000 samples/ sec per channel) are updated either synchronously or asynchronously, and support arbitrary waveform generation. The analog inputs are configurable as either 16 single-ended or 8 differential input channels, and can be scanned continuously or in bursts. Four digital outputs are also offered (output only). Inputs and outputs have a common software selected range of ±10V, ±5V or ±2.5V, and are accessed through independent 32K-sample FIFO buffers. Internal auto-calibration networks permit calibration to be performed without removing the board from the system. Software controlled test configurations include a loop-back mode for monitoring all analog output channels.

The 16AIO provides a cost effective high-speed 16-bit analog input/ output and digital I/O board. Four analog output channels (at 300,000 samples/sec per channel) are updated either synchronously or asynchronously, and support arbitrary waveform generation. The analog inputs are configurable as either 32 single-ended or 16 differential inputs, and can be scanned continuously or in bursts. Inputs and outputs have a common software selected range of ±10V, ±5V or ±2.5V, and are accessed through independent 32K-sample FIFO buffers. Internal auto-calibration networks permit calibration to be performed without removing the board from the system. Software controlled test configurations include a loop-back mode for monitoring all analog output channels.

Eight 16-Bit 0-20mA or 4-20mA scanned analog input channels, Software-configurable also as unipolar voltage inputs; 16 single-ended or eight differential, scaled as 0 to +10V, 0 to-+5V or 0 to +2.5V. Four 16-Bit current-loop output channels, configurable as 0-20mA or 4-20mA ranges, driven by four voltage-output DACs scaled as 0 to +10V, 0 to +5V or 0 to +2.5V. Both the current-loop outputs and the outputs of the voltage-DACs are available at the system I/O connector. Current-loop outputs have -15V to +11V compliance using internal supplies, or Zero to +31V compliance using an external +34V loop supply Independent 32K-sample analog input and output FIFO buffers 300K samples per second aggregate analog input sample rate ( 37 KSPS per channel for 8 active channels) 300K samples per second per channel analog output clocking rate (1200 KSPS aggregate rate) Multiple-channel and single-channel input scanning modes Buffer amplifiers on all analog input lines Supports waveform and arbitrary function generation, with continuous and one-shot modes 16-Bit bi-directional TTL digital port Internal rate generator controls input sampling, output sampling, or both simultaneously Supports multiboard synchronization of analog inputs and outputs Internal autocalibration of analog input and output channels Continuous and triggered-burst (one-shot) input and output Modes DMA engine minimizes host I/O overhead 68-Pin SCSI system I/O connector with metal shell 66MHz PCI support where applicable, with universal 5V/3.3V signaling

Analog Inputs: Two Differential Analog Inputs with dedicated 16-Bit ADC per channel True Simultaneous Sampling of all inputs to 2.0 MSPS per channel SAR Architecture; No minimum sample rate Analog Outputs: Two Single-Ended Analog Outputs with dedicated 16-Bit DAC per channel Simultaneous Output clocking rates to 2.0 MSPS per channel Selectable Direct-Write or FIFO-Buffered access Outputs-Disconnect feature ensures quiet, zeroed outputs during power-up and autocalibration Buffer Configurable as Open for data streaming, or Circular for periodic functions Common Analog I/O Features: Selectable Input/Output Ranges: ±10V, ±5V, ±2.5V Independent 2.0 Megasample input and output FIFO data buffers Hardware Clock and Sync I/O for multiboard operation Timing Controlled by internal rate generator, by software clocking, or externally 8-Bit Buffered TTL Digital Output Port: Eight TTL digital output channels 8x256K-sample data FIFO Clocking rates from Zero to 2MHz; Internal or external clock source General: 8-Bit Bidirectional TTL digital I/O port DMA Engine minimizes bus congestion Internal Power Conversion; Single 5-Volt power requirement Independent 24-Bit frequency dividers Internal Autocalibration 66 MHz 32-Bit PCI Support, with universal 5V/3.3V signaling Single-Width PMC form factor with integral EMI shield Extended-temperature version available

Analog Inputs: 8 Differential analog inputs with dedicated 16-Bit ADC per channel True simultaneous sampling of all inputs to 2.0 MSPS per channel SAR architecture; no minimum sample rate Analog Outputs: 4 Single-ended analog outputs with dedicated 16-Bit DAC per channel Simultaneous output clocking rates to 1.0 MSPS per channel Selectable direct-write or FIFO-buffered access Buffer configurable as open for data streaming, or circular for periodic functions Common Analog I/O Features: Selectable input/output ranges: ±10V, ±5V, ±2.5V Independent 256-Ksample input and output FIFO data buffers Hardware clock and sync I/O for multiboard operation Internal power conversion DMA engine minimizes bus congestion Timing controlled by internal rate generator, by software clocking, or externally Three independent 24-Bit frequency dividers On-demand autocalibration Front-panel system I/O access 16-Bit bidirectional TTL digital I/O port Conforms to PCI Express Specification revision 1.0a; x1 link operating at 2.5Gbps 3U VPX form factor

8 Differential 18-Bit Analog Input Channels DC to 500KSPS Sample Rate per Channel DC Accuracy: 0.005% Vsig + 0.003% FSR Group Delay: 8uS, 0-500KSPS, Maximum Continuous-Time 4-Pole Lowpass Filter; Selectable as Fc = 80kHz or 200kHz. Custom frequencies available. Inputs are software-configurable with or without 0-20ma current-loop input termination; 500 Ohms, 0.05%, 0.4 Watt, Individually selectable for each input channel. 100 dB Dynamic Range; Typical to 100 kHz with Fsamp = 400ksps 92 dB SINAD; Typical to 100 kHz with Fsamp = 400ksps 8 Single-ended or 3-Wire Differential 18-Bit Analog Output Channels DC to 500KSPS Sample Rate per Channel DC Accuracy: 0.005% Vsig +0.003% FSR Group Delay: 10us, 0-500KSPS, Maximum 95 dB Dynamic Range, Typical to 1MHz with Fsamp = 400ksps 90 dB SINAD, Typical to 1MHz with Fsamp = 400ksps Common Input/Output Characteristics: Software-Selectable Input/Output Ranges: ±10V, ±5V,±2.5V, 0 to +10V, 0 to +5V. Independent Input and output range selection. All inputs share a common input range, and all outputs share a common output range. Synchronous or Independent Input/Output Clocking Independent 1-MByte Input and Output FIFO Buffers; 2 MBytes total; Optional 2-MByte Input and Output Buffers; 4 MBytes Total Internal Sample Rate Generators 32-Bit Event Timer Hardware Sync and Clock I/O for Multiboard Synchronization 66/33MHz PCI support Conforms to PCl Bus Specification, Revision 2.3, with Universal Signaling Standard Full-Length PCI Form Factor DMA Engine Supports Block-Mode Transfers in Two Channels On-demand Autocalibration Ensures DC Precision as well as AC performance Integrated DC/DC Conversion and Dual Regulation for Internal Supply Voltages

The PMC-16AO4MFS D/A board provides 400KHz-per-channel precision high speed 16-bit analog outputs, and supports arbitrary waveform generation. Four analog output channels are updated independently from an internal buffer, either at software-determined rates, or by an externally supplied clock. Flexible operating modes include continuous, periodic and triggered burst functions, as well as the seamless, dynamic concatenation of waveforms in real-time. Output ranges are supplied as ±10V, ±5V or ±2.5V. Internal auto calibration networks permit periodic calibration to be performed without removing the board or host from the system. This feature produces the optimum calibration situation, in which the board is calibrated in its actual operating environment.

20 Precision High-Speed Analog Output Channels; 16-Bit Resolution; D/A Converter per Channel Data Rates to 400K Samples per Second per Channel; 8 MSPS Aggregate Rate Output Ranges of �10V, �5V or �2.5V Output Clocking Mode Selectable as Simultaneous or Sequential 256K-Sample Output Data Buffer Analog Output FIFO Buffer Software-Configurable as Open or Circular Continuous and Burst (One-Shot) Output Modes Support Seamless Waveform Sequencing Data Rate Controlled by Adjustable Internal Clock, or by Externally Supplied Clock Supports Multiboard Synchronization Optional Differential Clock I/O Available for Synchronizing Sigma-Delta A/D Boards On-Demand Autocalibration of all Channels Remote Ground Sensing High Accuracy; 0.017% FSR max error on �10V Range, INL = 0.007% Fast Settling; 5 us to 0.1%; 8 us to 0.01%;with No-filter Option